Asic Design Flow Using Synopsys Tools

EE5375 Synopsys Flow for ASIC

This flow only uses Synopsys tools from synthesis to place and route. However, the LVS and DRCs only work with Virtuoso and the associated checking tools. If anyone can get these to work with Synopsys' checking tools, please contact me - emac@utep.edu. The idea is for a university to be able to use the University of Utah's libraries with either tool suite.

To run Synopsys tools, you must use a C Shell and start with invoking the command "synopsys.env" which will set up your environment. Ask Nito if you have problems.

Lab 7 - ASIC Implementation

First, know that the libraries we will use are in /export/cadence/UofU_SYNS_v1_2. Explore this area and in particular the tutorials directory that should have a copy of all scripts, layermaps and tutorials.

n this lab, we will implement your MOSIS design as an 28 bond pad ASIC using Synopsys software.

Lab 7-A Synthesis using Design Compiler (required for MOSIS fabrication):

Synthesize your design using this file synthesis.tcl as a guideline to run dc_shell. Invoke dc_shell from the command line after updating your script with "dc_shell-t -f synthesis.tcl". This will provide a netlist, an SDC file and synthesis reports (area, timing, gates, etc.)

Email area and timing report to emac@utep.edu.

Lab 7-B Logic Core Place and Route with IC Compiler (required for MOSIS fabrication):

Implement your core with the following tutorial - icc_shell_tutorial_v3.pdf - and script - icc_ONC5_version3.tcl. The core should measure less than 950 micron per side (press K to invoke the ruler in IC Compiler). Show screen shots that verify that you have no DRC or LVS errors and that you have passed timing.

To read in your core gds you will need this file - UofU_TechLib_ami06_version2.layermap.

Email a screen shot of the final layout of your core with ruler to emac@utep.edu.

Lab 7-C Full Chip Integration with Custom Designer (required for MOSIS fabrication):

Integrate your core into the pad frame the following tutorial - cdesigner_v12.ppt.pdf The core should measure less than 950 micron per side (press K to invoke the ruler in IC Compiler). In your working directory make sure you include lib.defs, cds.lib, and display.tcl. Also, you can use this spreadsheet as a guide for your pinout - pinout.xlsx. This pinout is useful later to remember your pinout and if MOSIS rotates your chip it shows all four possible positions.

Email a screen shot of the final layout of your chip with ruler to emac@utep.edu.